FURSOY posts 500 MHz Linux-capable RISC-V core

FURSOY published Fursoy Slice-1 on GitHub on Nov. 14, a 64-bit out-of-order RISC-V processor design that its README says boots Linux 6.6.50 and targets 500 MHz.

The release matters for open chip development because the project pairs a 2-wide superscalar core with 8 of 8 standalone timing closures, according to the GitHub README; the repository showed 42 commits at capture.

The README describes the project as “A 64-bit Out-of-Order Superscalar RISC-V Processor” supporting RV64IMAFDV plus several RISC-V extensions. Out-of-order means the processor can execute ready instructions before earlier stalled ones; superscalar means it can handle more than one instruction in a cycle.

Fursoy Slice-1, listed as fursoy_s1_core and fursoy_s1_soc, is written in SystemVerilog and includes Sv39 demand paging, the README said. Sv39 is a RISC-V virtual-memory mode that maps virtual addresses to physical memory through page tables.

The design’s microarchitecture includes 2-wide fetch, decode, register rename and in-order retirement, according to the README. It also lists a 128-entry reorder buffer, a 160-entry physical integer register file, 8 branch checkpoints, 32-entry integer and memory issue queues, a floating-point issue queue and an 8-entry vector issue queue.

The memory subsystem is central to the claim that the core can boot a conventional operating-system stack. The README lists 64-entry instruction and data translation lookaside buffers, 16 KiB instruction and data caches, a shared hardware page-table walker and a 256 MiB DRAM interface, along with CLINT, PLIC and 16550 UART platform devices.

For physical synthesis, FURSOY said it evaluated 8 core functional blocks using Yosys 0.33, sv2v v0.0.13 and OpenSTA 3.1.0 on NangateOpenCellLibrary 45nm typical conditions at 1.10 volts and 25C. The README said all 8 blocks met a 2.000 nanosecond clock period, equivalent to 500 MHz, with total negative slack of 0.00 nanoseconds.

The largest listed standalone blocks were the data translation lookaside buffer, at 50,417 cells and 99.83 kGE, and the instruction translation lookaside buffer, at 36,238 cells and 77.12 kGE. Across the 8 standalone blocks, the README lists 111,019 cells, 14,836 flip-flops and 219.43 kGE.

The boot result is a simulation claim, not a commercial silicon disclosure. The README said a Milestone 9 closeout ran Linux 6.6.50 in Verilator for 89,861,075 simulated cycles, retiring 76,236,390 instructions, with 0 kernel panics, 0 oopses, 0 access faults and 0 CPI conservation errors.

The project’s own caveat is significant: the README said full-SoC place-and-route and SRAM macro compilation have not yet been executed. That means the published timing figures cover selected standalone blocks, not a completed chip implementation.

The Hacker News listing published Nov. 14 showed 5 points and 0 comments. The GitHub repository showed 1 branch and 0 tags, with the latest commit on Nov. 14 described as removing internal planning artifacts and finalizing the public tree.

Source: GitHub repository README and Hacker News listing, Nov. 14, 2026